法國(guó)巴黎高等電信學(xué)院2023年招聘博士后職位（多核架構(gòu)中的相互依存干擾）

巴黎高等電信學(xué)院，又名巴黎高科電信學(xué)院（Télécom ParisTech），原名為國(guó)立巴黎高等電信學(xué)院（ENST），是第一所主要從事信息科學(xué)與技術(shù)高等教學(xué)與研究的工程師學(xué)院，隸屬于巴黎理工學(xué)院，并且是巴黎高科（Paris Tech）、礦業(yè)電信學(xué)校聯(lián)盟（Institut Mines-Télécom）。

Post-Doctoral Fellow In Interdependent Interference In Multi-Core Architectures At Télécom Paris - 12 Months

Universities and Institutes of France

France

September 30, 2023

Contact:N/A

Offerd Salary:Negotiation

Location:N/A

Working address:N/A

Contract Type:12 months fixed term

Working Time:Full time

Working type:N/A

Ref info:N/A

22 May 2023

Job Information

Organisation/Company

Télécom Paris

Research Field

Other

Researcher Profile

First Stage Researcher (R1)

Country

France

Application Deadline

30 Sep 2023 - 00:00 (Europe/Paris)

Type of Contract

Temporary

Job Status

Full-time

Is the job funded through the EU Research Framework Programme?

Not funded by an EU programme

Is the Job related to staff position within a Research Infrastructure?

No

Offer Description

Who are we?

A school of the Institut Mines-Télécom, Télécom Paris is the leading French school for generalist digital engineers. With its excellent teaching and research, Télécom Paris is at the heart of a unique innovation ecosystem based on the transversality of its training, its research departments and its business incubator.

A founding member of the Institut Polytechnique de Paris, Télécom Paris is positioned as an open-air laboratory for all the major technological and societal challenges.

SCIENTIFIC CONTEXT

Software of (hard) real-time systems have to undergo rigorous verification of correctness, which includes verification whether the software meets all deadlines. An important aspect of this verification is timing analysis , which aims at determining a tight bound on the total execution time of a real- time computation (aka. task). A major challenge for timing analysis in multi-core systems is to determine the interference on the task's execution time by software running on other cores in parallel. This interference might be caused by shared resources, such as shared caches or shared buses, between the cores and may considerably increase the total execution time of a task. Another important phenomenon that may complicate this analysis are timing anomalies. These are situations where a locally favorable event during the execution of real-time software eventually leads to a global increase of the execution time. A typical example of such a situation is a cache hit (i.e., a hit is locally favorable compared to a miss since it takes less time) that impacts the way in which instructions are executed in an out-of-order processor pipeline (i.e., instructions are executed sequentially due to data dependencies instead of parallel). Both, multi-core interference and timing anomalies, may lead to state space explosion and may render the determination of safe execution time bounds practically impossible.

The objective of this post-doc position is to investigate the relationship between a) different sources of interference in multi-core architectures as well as b) multi-core interference and timing anomalies. In the later case we are interested in studying how to characterize interactions between different forms of interference. For instance, two memory requests originating from two different cores may interfere at the level of shared caches, shared buses, and eventually the shared memory. Naturally the interference at higher levels of the memory hierarchy may impose a (partial) ordering of memory requests. The objective his thus to study possible cancellation effects, but also possible amplification effects. Such amplification effects may, in fact, resemble timing anomalies and thus make it impossible to analyze the two sources of interference independently from each other.

The considered phenomena will be studied either directly by tracing executions on a suitable hardware platform or using abstract modeling/simulation (e.g. via model checking). Different scenarios of interdependent interference should be exposed and analyzed w.r.t their root causes in order to facilitate finding similar situations, e.g. on other hardware platforms. If time permits adapted analysis techniques that either take inter-dependencies into account should be developed or analysis techniques to (formally) analyze the characteristics of a hardware platform in order to rule out/detect such phenomena.

BIBLIOGRAPHY :

The Role of Causality in a Formal Definition of Timing Anomalies Benjamin Binder, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, and Mathieu Jan International Conference on Embedded and Real-Time Computing Systems and Applications https: // perso.telecom-paris.fr/brandner/paper/rtcsa22-binder.pdf

Is this Still Normal? Putting Definitions of Timing Anomalies to the Test

Benjamin Binder, Mihail Asavoae, Belgacem Ben Hedia, Florian Brandner, and Mathieu Jan International Conference on Embedded and Real-Time Computing Systems and Applications https: // perso.telecom-paris.fr/brandner/paper/rtcsa21-binder.pdf

Speculative Execution and Timing Predictability in an Open Source RISC-V Core Alban Gruin, Thomas Carle, Hugues Cassé, Christine Rochange Real-Time Systems Symposium https: // doi.org/10.1109/RTSS52674.2021.00043

A Survey of Timing Verification Techniques for Multi-Core Real-Time Systems Claire Maiza, Hamza Rihani, Juan Maria Rivas, Joël Goossens, S. Altmeyer, Robert Davis ACM Computing Surveys https: // doi.org/10.1145/3323212

Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core Systems Maximilien Dupont de Dinechin, Matheus Schuh, Matthieu Moy, Claire Maiza DATE 2020 https: // doi.org/10.23919/DATE48585.2020.9116460

CONTACT:

· Florian Brandner (florian.brandner@telecom-paris.fr)

· Claire Maiza (claire.maiza@univ-grenoble-alpes.fr)

· Hugues Cassé (hugues.casse@irit.fr)

JOB DESCRIPTION

POSITION RESPONSIBILITIES

1.Theoretical Exploration - Identification of sources of interference in multi-core systems. - Identification of sources that may be related to timing anomalies. - Identification of potential “cross talk” between interference mechanisms and timing anomalies.

2.Practical Evaluation - Analysis of actual computer architecture implementations (processors, SoCs, …) to demonstrate the presence of effects identified during the theoretical analysis. - Evaluation of the actual implication of the identified effects. Can the effects impact the correctness of timing analysis? Can interference mechanisms and timing anomalies influence each other eventually even cancel each other out?

3.Solution - Propose modifications to existing timing analysis techniques in order to take the identified effects into account. - Address potential issues with correctness of timing analyses (optimistic results or underestimation). - Exploit potential cancellation effects in order to improve analysis performance and/or precision.

4. Other activities - Participate in the ANR project CAOTIC (participation in meetings, talks, reporting activities, et cetera). - The position will collaborate with other CAOTIC partners at Grenoble and Toulouse. - If desired, candidates may participate in teaching at Télécom Paris.

Job requirements

Required skills, experience, and knowledge:

- Candidates need a PhD (or equivalent) preferably in a domain related to the topic (interference, timing analysis, real-time systems). - In addition profound knowledge of computer architecture design (processor cores, memory hierarchy) are required.

Other abilities and skills:

- A background in static program analysis (abstract interpretation, symbolic execution, ...) and formal methods (e.g., model checking) is important.

Candidates with the following qualifications may apply:

· PhD or equivalent

Why join us? You will work in a pleasant, green and accessible environment (especially for people with disabilities) only 20 km from Paris (RER B and C suburban train lines, proximity to major roads). You will benefit from many advantages (flexible working hours, possibility of telecommuting, proximity to sports facilities, concierge service, etc.).

Other information : Application deadline: 30/09/2023 Type of job : 12 months fixed term contract The position is to be filled by fall 2023. The successful candidate will work for the ANR project CAOTIC at Télécom Paris (Palaiseau, France) within the ACES team.

The application should be include:

- a detailed CV

- a letter of motivation

- any element considered useful for the examination of the application

Scientific contact : Florian BRANDNER florian.brandner@telecom-paris.fr

All our positions are open to people with disabilities.

Requirements

Research Field

Other

Education Level

PhD or equivalent

Additional InformationWork Location(s)

Number of offers available

1

Company/Institute

Télécom Paris

Country

Afghanistan

Geofield

Where to apply

Website

https: // institutminestelecom.recruitee.com/l/en/o/postdoctoral-fellow-in- interd…

Contact

City

PALAISEAU

Website

https: // www. telecom-paris.fr/

Street

19 Place Marguerite Perey

STATUS: EXPIRED

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